Power Constrained Design of Multiprocessor Interconnection Networks
نویسندگان
چکیده
[6] W. J. Dally, " Performance Analysis of k-ary n-cube interconnection networks, " IEEE Transactions on Computers, June 1990.
منابع مشابه
Performance Analysis of a New Neural Network for Routing in Mesh Interconnection Networks
Routing is one of the basic parts of a message passing multiprocessor system. The routing procedure has a great impact on the efficiency of a system. Neural algorithms that are currently in use for computer networks require a large number of neurons. If a specific topology of a multiprocessor network is considered, the number of neurons can be reduced. In this paper a new recurrent neural ne...
متن کاملPerformance Analysis of a New Neural Network for Routing in Mesh Interconnection Networks
Routing is one of the basic parts of a message passing multiprocessor system. The routing procedure has a great impact on the efficiency of a system. Neural algorithms that are currently in use for computer networks require a large number of neurons. If a specific topology of a multiprocessor network is considered, the number of neurons can be reduced. In this paper a new recurrent neural ne...
متن کاملPower/Performance Trade-offs for Direct Networks
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As multiprocessor systems become necessary to satisfy the computational requirements, interconnection network design will become subject to similar constraints. This paper focuses on the design of multiprocessor intercon...
متن کاملMathematical Model of Energy Consumption of A Hierarchical Shared Bus Interconnection Communication Network of an On-Chip Multiprocessor
Energy consumption is one of the performance issues in multiprocessor design. Apart from being critical for power critical systems, it determines the amount of heat dissipates by the system. That is, as the energy consumption rate reduces heat dissipation reduces. Many research efforts had gone into the different design schemes for reducing multiprocessors’ energy consumption. However, it has b...
متن کاملHierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor
Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohib...
متن کامل